The present invention relates to a frequency synthesizer device and a mobile radio device using the same and, more particularly, a frequency synthesizer device in which noises in the fractional-N system are reduced and a mobile radio device using the same.
The frequency synthesizer device is used to produce the carrier wave with any frequency from the reference signal. In the case of the mobile radio device, the frequency synthesizer device of high-speed lock up is requested to attain a high C/N and low power consumption in the intermittent reception, etc. In the case of the normal frequency synthesizer device, the setting interval of the output frequency of the voltage-controlled oscillator is limited by the comparison frequency of the phase comparator. In order to obtain the finer setting interval, the comparison frequency must be lowered, so that the lock-up time cannot be shortened. As the frequency synthesizer device that can reduce the lock-up time, there is the frequency synthesizer device that is called the fractional-N system.
A configuration of the frequency synthesizer device is shown in FIG. 21. In FIG. 21, PLL (Phase-Locked Loop) circuit 9 including a phase comparator 1, a low-pass filter (LPF) 2, a voltage-controlled oscillator 3 and a variable frequency divider 4 is provided in the frequency synthesizer device. The voltage-controlled oscillator (VCO) 3 is a circuit that oscillates a signal having a frequency in response to an input voltage. The variable frequency divider 4 is a circuit that frequency-divides the frequency of the output signal (fvco) of the VCO. The phase comparator 1 is a circuit that compares phase of an output signal (fdiv) of the variable frequency divider 4 with phase of the reference signal (fref) to output a phase difference. The low-pass filter 2 is a circuit that smoothes an output of the phase comparator 1. A frequency-division ratio control circuit 5 is a circuit that controls a frequency-division ratio by using the fdiv as a clock such that the frequency-division ratio is changed in time and a value of its time average contains a value below the decimal point.
The frequency-division ratio control circuit 5 comprises an accumulator portion 80, a fractional part calculator circuit 70, and a frequency-division ratio adder 6. The accumulator portion 80 is a circuit that outputs accumulated results of fractional part data, that are set externally, at a timing of fdiv. The fractional part calculator circuit 70 is a circuit that adds output results of the accumulator portion 80 every timing of fdiv. The frequency-division ratio adder 6 is a circuit that adds the result calculated by the fractional part calculator circuit 70 and integer part data that are set externally. The added result in the frequency-division ratio adder 6 gives a frequency-division ratio of the variable frequency divider 4. Because of control of this frequency-division ratio control circuit 5, there is no necessity that the frequency of fvco should be set to integral multiple of the frequency of fref. Thus, the frequency of fref can be set higher irrespective of the desired frequency interval in fvco. Therefore, the lock-up time can be reduced. At this time, if the frequency-division ratio of the variable frequency divider is simply changed periodically, frequency components of the change period are generated in the VCO output as spurious. In order to avoid this, as set forth in U.S. Pat. No. 4,609,881, Japanese Patent No. 2844389, and Japanese Patent Publication No. Hei 8-8741, for example, there is the approach employing a plurality of accumulators that are connected in multiple-stage fashion.
A configuration of the accumulator portions that are connected in multiple-stage fashion is shown in FIG.22. Each of the accumulators 801 to 804 having an adder and a register, and operates by using fdiv as the clock. The accumulator 801 at the first stage adds fractional part data that are set by the outside and an output of the register by using the adder, and then updates a value of the register. The accumulator 802 at the second stage adds an output of the register and an output of the adder in the accumulator 801 by using the adder, and then updates a value of the register. The accumulator 803 and the accumulator 804 perform the same operation as the accumulator 802. Behaviors of change in the operations of the adders and the clocks of the registers in the accumulators connected in this manner are shown in a timing chart in FIG. 23. The registers update the data supplied from the adders in synchronism with fdiv. The adder repeats the operation of the fractional part data and the output of the adder at the former stage, and then transmits the result to the later stage. In contrast, the adder in the accumulator outputs the carry signal of the most significant bit as the carry signal and then inputs it to the fractional part calculator circuit 70.
A configuration of the fractional part calculator circuit 70 is shown in FIG. 24. In FIG. 24, an adder 701 is a circuit that calculates the fractional part by adding binomial coefficients. The delay circuits 702 to 707 are circuits that delay the carry signals of the accumulators to generate sequentially the binomial coefficient represented by the Pascal""s triangle. The fractional part calculator circuit 70 operates with respect to the carry signals generated from respective accumulators as follows. That is, when the carry signal is input from the accumulator 801, the circuit generates +1. When the carry signal is input from the accumulator 802, the circuit generates +1 and then generates xe2x88x921 after one clock. When the carry signal is input from the accumulator 803, the circuit generates +1, then generates xe2x88x922 after one clock, and then generates +1 after two clocks. When the carry signal is input from the accumulator 804, the circuit generates +1, then generates xe2x88x923 after one clock, then generates +3 after two clocks, and then generates xe2x88x921 after three clocks. This behavior is shown in a timing chart in FIG. 25. The accumulators are operated at the timing of fdiv, and the adders overflows to output the carry signal. The delay units that are connected to the carry signals of the accumulator 802, the accumulator 803, and the accumulator 804 delay the carry signal every fdiv period using fdiv as the clock. The adder 701 adds the carry signals output at respective stages at the same timing of fdiv and outputs the result.
The frequency-division ratio adder 6 adds the integer part data that are set externally and the output of the adder 701. The result of the adder is the output of the frequency-division ratio control circuit 5 to set the frequency-division ratio of the variable frequency divider 4. This frequency-division ratio is changed substantially every timing of fdiv, whereby the frequency component in change of the frequency-division ratio is set high and thus the low frequency component is reduced.
The change in the frequency-division ratio caused by the carry signals that are generated from the accumulator 802, the accumulator 803, and the accumulator 804 become zero in time average respectively, and it does not affect the average frequency-division ratio. Therefore, only the carry signal generated from the accumulator 801 contributes the average frequency-division ratio.
However, in such frequency synthesizer device in the background art, all registers in respective accumulator portions update the data in synchronism with fdiv, and the adders perform the calculation in response to every data update in the registers and every change in the adder outputs in the former stages and then transmit results to the later stages. Hence, operations of a plurality of accumulators are concentrated to one timing, and the circuit operation time required for the transmission of the operation is extended. In the integrated circuit in which analogue circuits and digital circuits are integrated on the same semiconductor substrate, since the maximum power is consumed at change points of the clock for the digital circuits, potential of the semiconductor substrate and potential of the power supply are varied in synchronism with the clock. Therefore, there are problems such that variation in these potential generates the noise, degrades the C/N of the frequency synthesizer device, and prevents the realization of high C/N and high-speed lock-up.
Also, there is another problem such that, as the comparison frequency is set higher to put the feature of the fractional-N system to practical use, the noise generated by the frequency-division ratio control circuit is increased to increase the C/N degradation. In addition, there is another problem such that, if both the transmitter portion and the receiver portion are integrated on the same semiconductor substrate even though the characteristics as the frequency synthesizer device can be satisfied, the transmitting/receiving characteristics are degraded because of the interference of the noise generated by the frequency-division ratio control circuit. Further, there is another problem such that, if the lock-up time is delayed to assure the C/N, the power consumption in the intermittent operation of the mobile radio device is increased and also the standby time is shortened.
The present invention has been made to overcome such problems, and it is an object of the present invention to provide a frequency synthesizer device capable of reducing noises generated by a frequency-division ratio control circuit to improve a C/N ratio, reducing a lock-up time, and reducing a power consumption and a mobile radio device using the same.
In order to overcome the above subjects, in the present invention, there is provided a frequency synthesizer device comprising: a PLL circuit that includes a reference signal inputting means, a phase comparator, a low-pass filter, a voltage-controlled oscillator, and a variable frequency divider; and a frequency-division ratio control circuit including a plurality of accumulators for controlling the variable frequency divider such that a frequency division ratio of the variable frequency divider is changed in time and a time average value of the frequency division ratio contains a value below a decimal point and each having a register and an adder, a fractional part calculator circuit for receiving a carry signal generated by the adder to add binomial coefficients in sequence, and a frequency-division ratio adder for adding an output of the fractional part calculator circuit and integer part data to set the frequency division ratio in the variable frequency divider, wherein the frequency-division ratio control circuit is operated at a plurality of clocks having different timings, whereby a signal having a frequency that is equal to a product of the time average value of the frequency division ratio and a frequency of a reference signal is generated.
According to such configuration, the variation in the substrate potential and the variation in the power supply voltage generated by the operation of the frequency-division ratio control circuit can be reduced. Therefore, the degradation of C/N of the frequency synthesizer can be reduced, and also the lock-up time can be reduced. In addition, the power consumption in the intermittent operation can be reduced, and also the influence of the noises on other blocks constructed on the same substrate can be reduced.